1. Field of the Invention
The present invention relates to techniques for management of cache memories (also referred to herein as caches) in a data processing apparatus, and in particular to techniques for managing a hierarchy of caches in which at least two levels of cache at least in part exhibit exclusive behaviour with respect to each other.
2. Description of the Prior Art
A cache may be arranged to store data and/or instructions fetched from a memory so that they are subsequently readily accessible by a processor. Hereafter, unless otherwise apparent from the context, the term “data value” will be used to refer to both instructions and data. The cache will store the data value until it is overwritten by a data value for a new location required by the processor. The data value is stored in cache using either physical or virtual memory locations. Should the data value in the cache have been altered then it is usual to ensure that the altered data value is re-written to the memory, either at the time the data is altered or when the data value in the cache is overwritten.
As the size of a cache increases, the rate of achieving a cache hit within the cache increases. However, the larger the cache, the slower the cache will become. Another way to increase cache hit rate is to more effectively use the existing cache area. With this in mind, many modern designs use a hierarchy of caches, which allows a trade-off between optimising the hit time and miss rate. Different levels of cache within the hierarchy can be arranged to be either inclusive or exclusive. For example, considering a level one cache and a level two cache, an inclusive cache system implies that the contents of the level one cache are a subset of the contents of the level two cache. In contrast, an exclusive cache system is one in which the contents of the level one cache and level two cache are generally exclusive. By using an exclusive cache system, the effective cache size can be increased relative to an inclusive cache system, but typically the management of exclusive caches is more complex.
The article entitled “Performance Evaluation of Exclusive Cache Hierarchies” by Ying Zheng et al, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS04), Mar. 10-12, 2004, pages 89-96 provides a discussion of exclusive caching and inclusive caching systems.
Typically, more evictions of cache lines from the caches occur when employing an exclusive cache system rather than an inclusive cache system. This has an adverse effect on performance, particularly when certain of those evictions require data values to be evicted to main memory.
Accordingly, it would be desirable to provide a technique which enables the effective cache size increase resulting from use of exclusive caching systems to be realised, whilst reducing the number of evictions taking place when employing such an exclusive caching system.